Digital computers perform a variety of information processing tasks, the one is arithmetic operations. And the most basic arithmetic operation is the addition of two binary digits. i.e, 4 basic possible operations are:
0+0=0 0+1=1 1+0=1 1+1=10
The first three operations produce a sum whose length is one digit, but when augends and addend bits are equal to 1, the binary sum consists of two digits. The higher significant bit of this result is called a carry.
A combinational circuit that performs the addition of two bits is called a half-adder. One that performs the addition of 3 bits (two significant bits & previous carry) is called a full adder. And 2 half adder can employ as a full-adder.
A Half Adder is a combinational circuit with two binary inputs (augends and addend bits and two binary outputs (sum and carry bits.) It adds the two inputs (A and B) and produces the sum (S) and the carry (C) bits. It is an arithmetic operation of addition of two single-bit words.
Block Diagram :
Truth Table :
| Inputs | Outputs | ||
| A | B | S | C |
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
Expression Reduction For Sum (S) and Carry (C):
Without reducing the expressions with the K-Map, we can clearly write the expressions from the truth tables for Sum (S) and Carry (C). However, if you use a two-variable K-Map, you will be getting the exact same result.
S = A’B + AB’ = A ⊕ B
C = AB
Circuit Diagram :
A Full-adder is a combinational circuit that adds two bits and a carry and outputs a sum bit and a carry bit. To add two binary numbers, each having two or more bits, the LSBs can be added by using a half-adder. The carry resulted from the addition of the LSBs is carried over to the next significant column and added to the two bits in that column. So, in the second and higher columns, the two data bits of that column and the carry bit generated from the addition in the previous column need to be added.
The full-adder adds the bits A and B and the carry from the previous column called the carry-in Cin and outputs the sum bit S and the carry bit called the carry-out Cout. The variable S gives the value of the least significant bit of the sum. The variable Cout gives the output carry. The eight rows under the input variables designate all possible combinations of 1s and 0s that these variables may have. The 1s and 0s for the output variables are determined from the arithmetic sum of the input bits. When all the bits are 0s, the output is 0. The S output is equal to 1 when only 1 input is equal to 1 or when all the inputs are equal to 1. The C out has a carry of 1 if two or three inputs are equal to 1.
Block Diagram
Truth Table
| Inputs | Outputs | |||
| A | B | Cin | S | Cout |
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 1 |
Expression Reduction :
As seen in the below figures, the expression for the sum is not reducible, however, it can be simplified to a 3-input XOR form. Whereas, the output of the carry can be reduced :
Circuit Diagram :
Alternative Carry Expression :
Most of the time, another expression for carry is used that is obtained from a certain kind of special arrangement and reduction of the carry expression without the use of the K-Map. This is explained below and the reason behind generating a new expression is for the application for two half adders to function as a full adder.
From Truth table :
C = A’BC + AB’C + ABC’ + ABC
= C(A’B + AB’) + AB(C + C’)
= C(A ⊕ B) + AB
Circuit Diagram of full-adder with the new carry expression :
Full-Adder using two Half-Adders :
Now, let’s make use of the new carry expression that we have extracted from its standard SOP expression for implementing a full adder using two half adders.